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3D Integration- A Solution for next Generation Silicon Devices
Dr. Daniel Shi
3D integration is another major solution to increase IC density and functionality. Annual growth rate of all the 3D packaging is more than 24%, while the rate of the TSV based 3D packaging is more than 95%. 3D packaging/integration technology is believed to have many applications including consumer electronics, wireless communication, bio-medical devices, aerospace, and automotive, etc. ASTRI has established a comprehensive 3D packaging technology platform for HK/China packaging industry.
3D Integration A Solution for Next Generation Silicon Devices
Dr. Daniel SHI Applied Science & Technology Research Institute (ASTRI) Feb. 20, 2009
Background & Motivation Technology Development Status Worldwide Market Development Status & Forecast ASTRI's R&D in 3D Integration
Package-on-Package (PoP) Through-Silicon-Via (TSV)
Background & Motivation
Wire delay limits chip speed; Unclear if CMOS circuit possible under 32nm.
More than Moore
Reduce wire length to shorten delay; Stacked transistors to achieve faster CMOS circuit.
No suitable photolith system available; Unstable cell operation.
2011 2015: Intel / IBM
Use proven photolith system; Stable cell operation.
Difficult to make smaller capacitor; Longer wire delays.
2011 2015: Samsung
Smaller capacitor not needed; Shorter wires, leading to less delay.
Under 65nm may not lower cost; Difficulty in large DRAM.
2009 2010: Elpida
Lower manuf. Cost even with same 90nm; Stacking bigger DRAM by different processes.
DRAM + Logic 90nm
Problems with smaller design rule Advantages using 3D integration
End 2005: Sony
What is 3D Packaging?
2D Interconnect Die Stacking
SOC Solution Package-on-Package (PoP)
3D Interconnect Through Silicon Via (TSV)
TSV Chip (IBM: Apr. 13, 2007)
Shorten data-travel distances by up to 1000X; Allow for 100X more pathways than 2D chips; Sample 2Q'07 and production 2008.
WLAN; Source: IBM Cellular applications; High-performance server and supercomputer chips.
40% better power efficiency in SiGe-based wireless products; Increases processor speed by reducing grid power consumption up to 20%; Allows stacking of high-performance chips, e.g., processor-onprocessor or memory-on-processor.
Form Factor Motivation
Major Requirements of Future Electronic Products
Smaller, faster, thinner, & affordable, etc.;
Connect anywhere and anytime to information, entertainment, communication, monitoring and control.
Integrate different functional chips (RF, memory, logic, MEMS, imagers, etc.)
M an u f. C o st / b it (16-G b it = 100)
90 80 70 60 50 40 5Xnm Conventional smaller design rule 4X~3Xnm 3Xnm 3X ~2Xnm
Limit for further reduction; No photolith system available; Cell operation unstable.
< 2Xnm 30
3D Int. Moore R
3D integration of 2 memory cells
Moore rule continuity (cost drops ~40% / per bit with capacity increase.
16 32 64 128 256
NAND Flash Capacity (Gbit)
Technology Development Status Worldwide
Flash Memory Market Evolution
Flash Memory has many applications: PDAs, laptop computers, digital audio players, digital cameras and mobile phones, etc.
Source: Saifun Semiconductors
Flash Memory Players
NOR Flash Market Share (2006) NAND Flash Market Share (2006)
Samsung's Stacked Flash Memories
A small foot-print wafer-level processed stack package (WSP) 16Gbit memory prototype sample (Apr., 2006).
Samsung WSP technology
Vertically stacks eight 50um, 2Gb NAND chips, 0.56 mm in height TSV Formation (~ 30m diameter) : Laser Drill, Electroplating Via Filling Die-to-die bonding : micro-bump bonding Wafer Thinning : ~ 50m
NAND memory cards; other consumer electronics in early 2007; High-performance SiP solutions, high-capacity DRAM stack packages. ASTRI Proprietary
CMOS Imaging Sensor
CIS 1Q'07 Market Share
Source: Tech System Research ASTRI Proprietary
ST's TSV Interconnect
2MPixel (2.6x2.6um pixel) CIS: Leti & ST (Jun. 2007)
Photosensitive elements are placed on top of the CMOS circuit readout, allowing 100% light collection across the CMOS imager full die area; Key idea is to use hydrogenated amorphous silicon as the photosensitive layer element.
Camera cell-phone CMOS image sensors; Low light conditions: webcameras, surveillance cameras, etc.
Classical Architecture ASTRI Proprietary
Photosensitive elements are placed on top of the circuit read-out leading to ~ 100% light fill factor
Tessera's WLC Technology
50% size reduction; True chip size camera technology.
30% cost reduction; Reduces number of parts; Manual focus adjustment not needed.
From VGA to multiMega pixel resolutions; Compatible even when pixel size decreases.
Reflow-compatible materials used; Standard SMT assembly.
Available in both wire bond and BGA formats.
3D System Roadmap
Source: Yole Develop. 2007
Market Development Status & Forecast
Toshiba Image Sensor with TSV
Production started in January 2008. TSV Technology
Reduced wire bond substrate area by mounting components directly on the wafer and running electrodes through the vias on the circuit board, attached with solder balls; Reduced pixel size, contributing to 64% smaller size module.
3D Integration Forecast (1/2)
2006 Units (M) Wafer (x'000)
Notes: * All the 3D packaging; ** TSV based 3D packaging.
5000 4500 4000 Wafer (x'000) 3500 3000 2500 2000 1500 1000 500 0 2006 2007 2008 2009 2010 2011 2012
4000 3000 2000 1000 0 2006 2007 2008 2009 2010 2011
Source: ETP 2007 ASTRI Proprietary
Source: Yole Development 2007
3D Integration Forecast (2/2)
Flash & DRAM memories show big potential market with high growth rate.
5000 4500 4000 3500
3D-SiP Logic (12'' eq.) MEMS (8'' eq.) DRAM (12'' eq.) Flash (12'' eq.) CIS (12'' eq.) RF-SiP (8'' eq.)
3000 2500 2000 1500 1000
Source: Yole Development 2007
500 0 2006 2007 2008 2009 2010 2011 2012
RF-SiP (8'' eq.) CIS (12'' eq.) Flash (12'' eq.) DRAM (12'' eq.) MEMS (8'' eq.) 3D-SiP (12'' ASTRI Proprietary eq.)
19.77 68.06 0 0 0 0
37.58 92.63 0 0 4.56 0
54.38 106.53 164.94 6.04 31.19 0.42
71.19 136.15 583.73 46.01 61.41 3.02
88 164.45 1087.35 189.44 108.98 10.63
104.81 182.13 1946.4 513.34 184.87 28.16
121.62 194.92 3391.65 857.07 291.72 64.26
35.40% 19.20% 112.90% 245.20% 129.80% 251.30%
3D System Application Forecast
Cellular phones are dominant application
3% 3% 7% 1% 2% 5% 3% 2% 69%
Cell Phone PDAs Camcorders Digital Cameras PCs Servers/Workstations Base Stations MP3 Players Digital Video Recorders Laptop computers Internet Routers/Switches Other
Ultra-mobile PC (processor, memory, ASIC, RF) Portable TV (processor, memory, ASIC, RF) Play station portable (processor, memory, GPU, RF) Mobile phone (processor, memory, ASIC, RF) Digital camera (ASIC, memory) Digital video products (GPU, memory) Imaging sensor module (image sensor, DSP, SRAM)
3D Interconnect Forecast
WL-CSP & TSV
TSV will aggressively take over more and more market shares.
ASTRI's R&D in 3D Integration
ASTRI's R&D Focus (1/2)
3D Packaging Development Cycle
Materials Process Qualification Testing
* DFR Design for Reliability DFM Design for Manufacturability
ASTRI's R&D Focus (2/2)
Reliability Engineering for 3D Packaging
PoP 3D Pkg
WB 3D Pkg
TSV 3D Pkg
e pm velo e nD orte Sh
e Tim ycle tC
PoP Based 3D Packaging (1/5)
Manufacturability & Reliability Issues in PoP
Warpage: top & bottom module warped differently causes the failures in the solder joints; Stand-off: the reduction of solder joint pitch results in the stand-off issue.
Current Solutions New PoP Package
Polymer Core Bump PoP
Molded Cu Bump PoP
PoP Based 3D Packaging (2/5)
1ST DS* 1ST WB* 2ND DS* 3nd DS* 2ND WB* Encap. Molding Solder Reflow
Top Package Solder Reflow Bottom Package
* DS Die Stacking; WB Wire Bonding.
PoP Based 3D Packaging (3/5)
P1 Package Design P2 P3 P4 P5 P6 P7 P8 P9 T1 T2 T3 T4 T5 T6 T7 T8 T9 Yes Package Fabrication
No Pkg Design Related Solutions (DFM / DFR)* No
*< Non-Package CT Design Issues D
ths on 6M
Qual. & Relia.
Materials / Process Related Solutions (DFM / DFR)*
P1, 2, 3 ... -- the packaging processes, e.g., die stacking, encap. molding, reflow, etc.; T1, 2, 3 ... the testing methods, e.g., precon., thermal cycling, humidity, bake, drop, etc.; DFM Design for Manufacturability; DFR Design for Reliability; DCT Development Cycle Time.
PoP Based 3D Packaging (4/5)
PoP Based 3D Packaging (5/5)
db u ce h s ed nt Bottom viewr as mo e w in 3 pag ith ar w W
3x3 top PoP module
Substrate for PoP
9 mounted PoP modules
TSV Based 3D Packaging (1/6)
TSV Based 3D Packaging (2/6)
DRIE-Based Via Drilling
Different kinds of via shape; Different diameters of 25, 50, 75, and 100um.
Circular via hole with diameters of 25, 50, 75, and 100um
Isotropic etching: experiment (left) and simulation (right)
Square via hole with sizes of 25, 50, 75, and 100um
Anisotropic etching: experiment (left) and simulation (right)
TSV Based 3D Packaging (3/6)
Electroplating Based Via Filling
Simulation: Cell-design for electroplating; ANSYS for thermo-mechanical design. Bottom-up electroplating process.
TSV via bottom-up filling process simulation (Cell Design)
A '' TSV wafer
Top view of single chip X-section view of three vias with the aspect ratio of 6 and fully filled with Cu.
TSV via thermo-mechanical simulation (ANSYS)
TSV Based 3D Packaging (4/6)
Wafer Thinning & Thin Wafer Handling
Wafer bonding & thin wafer handling Mechanical grinding + chemical mechanical polishing (CMP) + dry etching
Special adhesive used to bond the wafer to the holder
A bendable memory wafer with thickness of 75um Methodology for wafer thinning process development
TSV Based 3D Packaging (5/6)
Pulse Laser Bonding Technology
Stacking Method Wafer to Wafer Flexibility Yield Throughput Bonding Technology Diffusion Bonding Tezzaro n Chip to Wafer Chip to Chip Middle High Middle High Middle Low Companies Intel MIT More n More Solder Bonding IZM ASET Infineo
Adhesive Bonding RTI RPI Tohoku DARPA More
Wafer/Chip Isolation Layer ASTRI Proprietary
Metal 1 Polymer Metal 2
Cu-Cu diffusion bonding (IBM)
Pulse laser bonding demonstrating low residual stress & high throughput.
TSV Based 3D Packaging (6/6)
Design Advisor TSV Stacking PoP Stacking
Electrical performance short interconnect, less power consumption; Substrate shielding eliminate EMI between digital & RF; Interposer high density I/O redistribution & mechanical support;
Structure symmetry minimal warpage; IMC interconnect minimal warpage, good reliability; PoP easy for testing; Low cost less process;
3D integration/More Than Moore is another major solution to increase IC density and functionality; Annual growth rate of all the 3D packaging is more than 24%, while the rate of the TSV based 3D packaging is more than 95%. 3D packaging/integration technology is believed to have many applications including consumer electronics, wireless communication, bio-medical devices, aerospace, and automotive, etc. ASTRI has established a comprehensive 3D packaging technology platform for HK/China packaging industry.
Many thanks to Innovation & Technology Commission (ITC), HKSAR for financial support to this study; Special thanks to Advanced Packaging Technologies (APT) team in ASTRI for their great contributions to this work.
Visit us at: www.astri.org or Contact us: Mr. Lawrence CHAN Tel: (+852) 3406 2661 Email: email@example.com
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