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    Exploiting Extended FD-SOI DVFS & Body-Bias Capabilities: Architectural Choices & Design-Implementation Methodologies

      David Jacquet
     Apr 3, 2014
    Description:

    This electronic document is present How to increase the energy efficiency of SOCs & CPUs ? And more about Exploiting Extended FD-SOI DVFS & Body-Bias Capabilities. Design can remain synchronous - Split array/periphery memories might be needed for wide DVFS voltage range. To make Communications between voltage domains than i need level sifters, Asynchronous communications and System consequences with Extra latency on communications versus fully synchronous communications. increase the energy efficiency of computing systems with several Technique like Increasing the # of processing cores limitations in bulk leakage current for a given performance. A new process & design techniques are needed In any technology node, a trade off must be made between speed and leakage at a given voltage with the maximum speed can be increased at the expense of higher leakage. In FD-SOI, the wide Body-Bias range allows this trade off to be dynamically optimized to the conditions. FD-SOI & multiprocessing provides more performance at same voltage as bulk. We have demonstrated that FD-SOI enables dynamic management of the leakage / dynamic-power tradeoff.

    Important Tags: Body-Bias Capabilities, Design Implementation Methodologies, Free publish, electronics presentations
    Views: 5337
    Domain: Electronics
    Category: Semiconductors


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