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    Fins And Wires, How Do We Get To 5nm?

      Michael Chudzik
     Sep 14, 2016
    Description:

    FinFET Scaling to 7nm: Traditional Intrinsic Device Improvement- Device width increase: Taller FinFETs, Narrower FinFET: reduced well doping = higher mobility and gate scaling, Higher strain in epitaxial S/D. Extrinsic Resistance & Capacitance Reduction- Fin depopulation: More aggressive cell height while enabling relaxed Fin pitch scaling, Low-k spacers, BEOL ULK/Air-gap, etc, Contact resistance improvements, Move to Co, Area enhancement S/D silicide, Improved conformal SDE doping. Variability Reduction- Improve the slow corners of the device to reduce speed variance, RDF reduction: New isolation, scaled fin width, thermal budgets, etc.

    Important Tags: Technology roadmap, Applied materials, Strain engineering, FinFET technology
    Views: 2314
    Domain: Electronics
    Category: Semiconductors


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