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Freescale's MRAM Explored
Freescale's MRAM Explored
After looking at John Sansing's presentation on the MRAM (posted on 03/08/07), I thought that might be apposite to give a little more detail about this device and provide some images of the structure of the Freescale MR2A16ATS35C 4.2-Mbit device that we looked at. As Freescale has detailed in their publications, the core cell of an MRAM device is a magnetic tunnel junctio
(MTJ). The bit state is stored as the relative magnetization orientation of the two magnetic layers in direct contact with a tunnel barrier, with the anti-parallel orientation (high state) having a higher junction resistance than the parallel orientation (low state). The bit state is read out by passing a current through the junction and comparing the junction voltage to a known reference voltage1.
Fig. 1. Freescale MRAM Magnetic Tunnel Junctions, Top View
The Freescale MRAM cell has these multilayer magnetic tunnel junctions placed diagonally between two high-current write line conductors which are formed in metal 4 and metal 5, and arranged at right angles to each other. In Figure 1 above, we can just see the lower write lines under the array of junction plates. The contacts seen at the top of each plate go down to an isolation (select) transistor in the substrate. In the image (Fig. 2) below, we can see the lower M4 write lines in cross-section, and a linear section of an upper M5 write line, with the magnetic tunnel junction structure in between.
Fig. 2. SEM Cross-Section of MTJ structure (some sample prep artifacts present)
Figure 3 below illustrates the principle of operation. The device employs magnetoresistive tunneling across an insulating tunnel barrier, sandwiched between two synthetic antiferromagnetic (SAF) layers. The top SAF layer is "free" (i.e. its magnetic moment can be programmed), and the bottom SAF is a "fixed" (not programmable) reference layer.
Fig. 3. Schematic of Magnetic Tunnel Junction Structure
In both cases the SAF layer is actually three sub-layers, two ferromagnetic layers separated by a non-magnetic spacer; the free ferromagnetic sub layers use a magnetically programmable material with almost balanced magnetic moments. This allows the magnetic moments to rotate like a pair of linked "clock hands" when the magnetic field is applied. The tunnel barrier is aluminum oxide. This multiple layer structure is shown in Figure 4.
Fig. 4. TEM Image of the MTJ Structure
The use of this type of structure, in its diagonal orientation, allows the magnetic moments to be toggled 180o using the same two-phase pulse sequence regardless of state, using both write lines; this requires a pre-read to see if a write sequence is needed, but protects the datum state from a single pulse on either one of the write lines (see sequence below).
Fig.5. MRAM Toggle Switching Sequence (source: Freescale)
The write lines themselves have some interesting structural quirks to optimise the magnetic coupling to the MTJ. Not the least interesting is
that they are made of copper; whereas the bond pads and lower metal layers are the conventional aluminum consistent with the 0.18- m process used. Presumably this is to allow higher current density, to give a higher magnetic field and keep the cell pitch down. The inlaid damascene structure also aids the use of magnetically permeable cladding layers which concentrate the magnetic fields Freescale claimed double the magnetic flux when these layers were added2. The cladding in the bottom write line focuses the magnetic field upwards into the tunnel junction. This is elegantly achieved by adding a NiFe layer to the barrier layer structure of the damascene line, seen schematically in Figure 3, and in TEM cross-section in Figure 6. The NiFe is laid down as an outer barrier layer, and then the usual Ta-based barrier before filling the trench with copper.
Fig. 6. TEM Images of the M4 Write Line Structure
The upper write line is more difficult to make, since to focus the field down on to the MTJ we need to have the cladding on the top and sides of the line (see Figure 3). Figure 7 illustrates how Freescale achieved this they put down a Ta barrier layer, followed by the NiFe layer, on the bottom and sidewalls of the trench; then the NiFe is sputtered away from the trench bottom and another Ta barrier layer deposited. The trench is filled with copper and planarized as usual, and nitride and oxide metal cap layers are deposited. These are masked and etched to expose the top of the M5 copper in the memory array; a second set of NiFe and Ta layers are deposited; and then polished back to remove the excess and isolate the lines, leaving "wings" at each line edge. As we can see, a relatively complex process, but it achieves the desired end.
Ta NiFe M5
NiFe Ta Ta
Fig. 7. TEM Images of the M5 Write Line Structure
That covers the basics of the MTJ as noted above, the part itself is fabbed in a 0.18- m CMOS process, using three layers of aluminum metallization under the write lines, plus an aluminum bond pad layer. This makes it one of the few parts that we have seen with a true hybrid metallization structure, as distinct from the copper metal with Al bond pads that we see in most 130-nm and smaller parts. This actually is a clue to the fab history of the part; when we looked at the front-end structure (i.e. transistors + M1 M3), it looked VERY like TSMC's 0.18- m process that we've seen in quite a few other devices. Discreet inquiry revealed that the front end was indeed fabbed out to TSMC, and then the wafers were shipped back to Chandler to add the MRAM structure. Given that the Freescale marketing team has been saying that a major advantage of this MRAM technology is that it is a back-end addition to conventional CMOS, and therefore very suitable for embedded use, this fab sequence would seem to be a clear demonstration of that statement. And as I think about it, as a manufacturing strategy, it also makes a lot of sense, since it keeps the wafer cost down to foundry levels, and also allows tighter inventory control for a speculative product launch keep a stock of front-end wafers, and only add the back-end as needed by order volume. The MRAM cell size of 1.3 m2 compares well with SRAM cell sizes of that generation one of the target markets is battery-backed SRAM storage used for applications such as data logging, and the device is packaged with an SRAM-compatible pinout. With this part, Freescale has come up with a fascinating technology which could have some disadvantages in terms of price/performance, but as a
solution that requires zero power to store data it will find some interesting applications in automotive, aerospace, and similar markets. References: 1. P.K. Naji et al., "A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM", IEEE ISSC Dig. Tech. Papers, vol 44, Feb 2001 2. M. Durlam et al., "A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects", 2002 Symposium on VLSI Circuits, Paper 12-4 Acknowledgement I would like to thank Chipworks' laboratory staff and process analysts, who actually did all the hard work of analyzing this device. N.B. The text for this paper was drawn from a blog posted at http://www.chipworks.com/blogs.aspx?id=2514 and a Chip Forensics article in the March '07 issue of Solid State Technology.
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