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    Iterative, Layered and Latticed ECC

      Oliver Hambrey
     Mar 18, 2015
    Description:

    Layered- MAIN ECC (BCH), INTRA PAGE ITERATIONS, READ RETRY, NEIGHBOUR PAGE ITERATIONS, LATTICE ECC, HIGHER LEVEL RECOVERY. Rule of thumb: Enter next layer with frequency at most 0.1/x x is the increase in latency between current and next layer. Lattice ECC Correctability- 1x TLC NAND, over 2 million pages analysed, lattice size: 129 pages, 128 info pages, 1 parity page, 1 page correctable guaranteed, up to 8 pages correctable more than 90% of the time. Summary- Iterative methods based on hard BCH decoding: powerful error correction, no change in code rate, low silicon cost, negligible impact on average latency. Powerful Lattice ECC: guaranteed correctability of r bad pages with r parity pages, more than guaranteed correctability in many cases. Siglead’s iterative BCH engine: powerful, low latency, iterative hard ECC, significant endurance and lifetime gains for sub 20nm NAND. SSD controller SL2007(8): SATAIII, 8(16) CE/channel, Siglead’s iterative BCH engine. SigNASII/III: NAND Flash Memory evaluation, ADC/DAC evaluation board Sp9907: AD converter 12bit 550Msps 2channel, DA converter 16bit 1Gsps 2channel.

    Important Tags: Layered and Latticed ECC, SSD ECC
    Views: 3026
    Domain: Electronics
    Category: Semiconductors


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