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    LDPC Codes for NAND Flash

      Xinde Hu
     7th-Jun-2016
    Description: Introduction to Low-Density Parity Check Codes: Near capacity error correcting performance, Iterative BP decoding algorithm requires soft information (LLRs) to reach maximum error correcting capability, Challenges- Performance cannot be characterized theoretically (large simulation required), Code design to avoid error floors, Low complexity implementation of LDPC decoder. LLRs from NAND Flash: Each cell is binned by applying multiple read threshold levels, Different reliability values(LLRs) are assigned to cells in different bins. Key challenges- Optimal read level settings change as flash memory ages, Negative read levels.
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    Views: 1456
    Domain: Electronics
    Category: Semiconductors
    Contents:
    LDPC Codes for Flash Channel
    Xinde Hu
    xhu@stec-inc.com

    Flash Memory Summit 2012
    Santa Clara, CA

    1

    Outline
    • LDPC codes for NAND Flash – Introduction
    • LDPC-based flash channel for enterprise SSDs –
    Challenges and Solutions
    • Flexible and efficient implementation of LDPC-code
    for Flash channel
    • Conclusions

    Flash Memory Summit 2012
    Santa Clara, CA

    2

    Introduct ... See more