Capacity utilization is expected to rise in March as the industry comes off its normal holiday production weakness, according to a recent Chip Insider® Graphics report from VLSI Research. Tester utilization is being driven up by an expansion of device complexity from 16/14nm node production ramp. Here the combination of more transistors and lower yields is driving up test times, which eats away at test capacity. Both assembly and test utilization is being driven up by the industry’s move to advance packaging, which requires new tool capability. In addition to these drivers, Wafer Fab utilization is being also being driven by the transition to the 10nm node in early logic production and the much anticipated 3D NAND ramp.
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