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SRC GRC University Research Highlights November 2007
Dale Edwards, William Joyner, Kwok Ng, David Yeh, Scott List, Harold Hosack, Alan K. Allan
Research Highlights for the Month of November 2007
Computer Aided Design & Test Sciences
Technical Thrust: Logic & Physical Design Research Highlight: Report on the Design and Simulation of Modified Test Structures for Extraction The previously fabricated high frequency substrate coupling test structures has been extensively characterized to identify their shortcomings. Based on the experimental
haracterization and electromagnetic simulations a modified test structure is developed. Oregon State University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Efficient Safety Check for Power Grid Optimization Voltages on the power/ground distribution network (grid) on an integrated circuit under go significant variations around their ideal values due to the grid resistance and inductance. As part of integrated circuit verification, one should check if such fluctuations on the grid exceed some critical threshold. This is of importance since excessive voltage variations on the grid are detrimental to circuit timing and can lead to either intermittent soft-errors or to non-functional chips. As part of the target framework for optimization, the researchers have focused on developing an efficient safety check for grids modeled as RC and RLC structures. Such a safety check would be essential to any optimization strategy because the verification approaches so far under both grid structures have been too slow for use inside an optimizer as they require performing an optimization at every time step until convergence. Recently, the team was able to transform the verification problem, using a geometric approach, from an optimization problem that requires as many linear programs as there are power grid nodes, to another involving a limited number of solutions of one linear system. Univ. of Toronto SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Report on the Results of Experimentation with Statistical Optimization Tools This report summarizes the experiments that the researchers carried out to study the practical issues associated with the use of formal probabilistic design strategies. Specifically, they investigate the properties of statistical optimization based on second-order conic programming (SOCP) that they have developed earlier. Optimization based on SOCP offers significant computational benefits compared to other statistical optimization methods. At the same time, several difficulties related to achieving timing closure in the context of statistical timing evaluation remain. A specific challenge is the difficulty of choosing the initial conditions for running the SOCP, which seems to require non-trivial yield-budgeting to be implemented. In this report, they summarize our efforts to shed light on the appropriate yield-budgeting strategies. Univ. of Texas/Austin SRC Contact: W. Dale Edwards (Dale.Edwards@src.org)
www.src.org GRC is a program of Semiconductor Research Corporation P.O. Box 12053, Research Triangle Park, NC 27709
Technical Thrust: Test and Testability Research Highlight: Generation of Instruction Sequences for Testing of Datapath Units of a Microprocessor An automatic functional test generation procedure for processors at the chip level based on property-based operators. The output generated consists of instruction sequences each generated for a different module of the processor and aimed at achieving a high gate-level fault coverage for the module. Purdue University SRC Contact: William H. Joyner (email@example.com) Research Highlight: Test Response Compaction using Single Output Compactors In order to achieve maximal reduction of test data volume, not only the test stimuli must be compressed to reduce the test data to be loaded, but also the test responses need be compacted to reduce the amount of unloaded test data. The test response compaction using a single output achieves maximal compaction. Such compactors accept data from several (all) scan chains producing compacted response data on a single pin (output). The researchers briefly discuss how such compactors can be constructed while describing in detail one compactor that uses a tree of exclusive OR gates as a compactor. Univ. of Iowa SRC Contact: William H. Joyner (firstname.lastname@example.org) Technical Thrust: Verification Research Highlight: Report on the Software for Detecting Violation of Safety Predicates using Manual Instrumentation This report describes the software and the underlying algorithms to detect violation of temporal predicates, including safety properties. The software is based on the idea of efficiently computing a 'basis' of the computation with respect to the original computation. The verification process is initiated by manually instrumenting the distributed program or system level hardware design. The instrumentation consists of logging and timestamping (with vector clocks) all communication and internal events in the independently executing threads or processes. The values of all the pertinent variables in the property to be detected are also logged to a file. The software, Basis Temporal Verifier (BTV), processes the offline trace files thus generated. The trace files are in a simple human readable text format. The predicate can be any valid BTV predicate and is specified in another text file in an easily readable format. BTV verifies the trace in polynomial time with respect to the size of the trace. Univ. of Texas/Austin SRC Contact: William H. Joyner (email@example.com) Research Highlight: Report on the Development of a Word-Level Quantification Engine A decision procedure for a logic is an algorithm that reports whether a formula given in that logic is satisfiable or unsatisfiable. A typical verification flow makes at least one (and usually many) decision procedures queries. Thus, having efficient decision procedures is crucial for obtaining scalable verification tools. Most hardware and software verification techniques generate decision procedure queries in a logic known as bit-vector arithmetic. The formulas in this logic contain finite precision variables (bit-vectors), arithmetic operations over bit-vectors, and bit-wise operations (such as concatenation, extraction, shifting) over bitvectors. The authors describe the existing work on decision procedures for bit-vector arithmetic and the work we are doing below.
Carnegie Mellon University SRC Contact: William H. Joyner (firstname.lastname@example.org)
Technical Thrust: Device Sciences Modeling & Simulation Research Highlight: Solid Phase Epitaxy in Uniaxially-Stressed (001) Si The effect of  uniaxial stresses up to 1.5 GPa on defect nucleation during solid phase epitaxy of amorphous (001) Si created via ion implantation was examined. The solid phase epitaxial regrowth velocity was slowed in compression. However, in tension, the velocity was unaffected. Both compression and tension resulted in an increase in regrowth defects compared to the stress-free case. The defects in compression appear to arise from roughening of the crystallizing interface whereas in tension it is proposed that reorientation of crystallites near the initial amorphous/crystalline interface is responsible for defect formation. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Influence of As on the Formation of Mask-edge Defects During Stressed Solid Phase Epitaxy in Patterned Si Wafers The influence of As on the evolution of mask-edge defects during stressed solid phase epitaxy of two-dimensional Si pre-amorphized regions in patterned Si wafers was examined. Mask-edge defects ~60 nm deep formed at 525 degrees C for As(+) implant energies of 7.5 - 50 keV with peak As concentration of ~5.0x10(20) cm(-3). Defect formation was attributed to an As-enhanced  regrowth rate relative to the  regrowth rate creating an amorphous/crystalline interface geometry favorable for defect formation. The similarity of mask-edge defect depths with As implant energy was attributed to surface retardation of  regrowth in shallow implants and enhanced  regrowth in deeper implants. Results indicate stress effects on regrowth rates are small compared to dopant effects. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Technical Thrust: Digital CMOS Research Highlight: Schottky Barrier Height of PtSiGe Contacts Formed on Si(1-x)Ge(x) Alloys In this study, the researchers have measured the Schottky barrier height of platinum germanosilicide contacts formed on p-type SiGe alloys. The SiGe layers used in this study were grown by ultrahigh vacuum rapid thermal chemical vapor deposition. The impact of Ge concentration (0 to 48%) as well as the in-plane biaxial compressive strain in the epitaxial layers were considered as variables. The results indicate that the barrier height is independent of the strain in SiGe and increases with Ge concentration in the alloy. It is shown that the barrier height varies from 0.22 eV on pure Si to 0.41 eV on SiGe with 48% Ge. North Carolina State University SRC Contact: Kwok Ng (Kwok.Ng@src.org)
Technical Thrust: Memory Technologies Research Highlight: Nanoscaled SONOS/NROM Nonvolatile Semiconductor Memory (NVSM) II High-K, ALD deposited, Al(2)O(3) has been employed as the blocking oxide in Lehigh-fabricated SANOS nonvolatile memory (NVSM) transistors. An improved memory window and retention has been achieved at 10 years (1.5V) with low program/erase voltages (<8V). These devices show good endurance performance to 1E6 stress cycles. The trap density of the silicon nitride is obtained from retention analysis and is approximately 6E18 traps/cm(3)eV. A speed simulation model has been developed and extended to model charge transport in multi-dielectric SONOS devices. Simulations on Lehigh MANOS and reported advanced commercial 32Gb TANOS devices agree with observed electrical characteristics. A mask set has been designed and fabricated to use in a capacitance flatband tracking system. This system will be employed to evaluate erase/write and retention characteristics of ONO and ANO stacks, which require only a few lithographic and process steps. Lehigh University SRC Contact: Kwok Ng (Kwok.Ng@src.org)
Integrated Circuits & Systems Sciences
Technical Thrust: Circuit Design Research Highlight: Ultra Low-voltage Analog-to-digital Converters in Submicron CMOS This research update summarizes the work of three ongoing projects. Measured results from a 12-bit pipelined A/D converter using correlated level shifting (CLS) are presented; the debugging progress of the SMASH delta-sigma A/D converter is presented; and the research progress of the comparator based delta-sigma is given. Oregon State University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Final Report Detailing the Design and Testing of an Integrated Circuit Testchip to Validate the Concepts Developed in this Task and the Accompanying Task Focusing on Global Serial Communication Between Asynchronous Modules Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this project, the authors present a novel power-gating scheme for repeaters on global bus lines that addresses the problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. The authors propose using a pulsed MTCMOS scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling, which effectively negates the power-gating and pulse generation performance penalty. The researchers consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. The bus system prototype is implemented in an industrial 65-nm SOI technology and measured results show up to a 45% reduction in total bus system power and an average reduction of 2.4X in standby mode leakage power.
Univ. of Michigan SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: A Low-Area Interconnect Architecture for Chip Multiprocessors A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, a proposed statically configurable asymmetric architecture assigns large buffer resources only to the nearest neighbor interconnect and much smaller buffer resources for long distance interconnect. To maintain flexible routing capability with low cost, each neighboring processor pair has two connecting links. Compared to a traditional dynamically configurable interconnect architecture with symmetric buffer allocation and single-links between neighboring processor pairs, this implementation has approximately 2 times smaller communication circuitry area with similar routing capability. Area and speed estimates are obtained with the physical design of seven chips in 0.18 um CMOS. Univ. of California/Davis SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: A 70mW 320MS/s 10-bit ADC in 0.13um Digital CMOS ADCs with high sampling frequency (>100MHz) and high SFDR (>70dBFS) at high input signal frequency are widely used today in many applications such as wired and wireless communications, medical instrumentation, and tests and measurements. The market for high-volume consumer electronic products demands highly integrated, low cost and low power System-on-Chip (SOC) solutions, which typically must use the latest deep-submicron digital CMOS process to achieve low power consumption and high levels of integration with both analog and digital circuitry. The pipeline architecture, which has been exclusively used for these high sampling frequency >8b resolution ADCs, is difficult to implement in deep-submicron CMOS processes due to the degraded transistor linearity, reduced voltage gain and smaller voltage headroom. This is mainly because accurate analog residue signal amplification is needed between stages. Analog techniques such as multi-stage amplifiers and nested gain boosting were frequently used, which degrades the settling time and limits maximum sampling frequency. In this research project, we propose a novel architecture that is similar to conventional two-step subranging architecture to achieve higher performance (better SFDR, lower power and higher sampling frequency) than pipeline ADCs with deep submicron meter digital CMOS process at 10b resolution. The proposed ADC consists of a "coarse" flash ADC that determines a rough range of the input analog level and switches reference levels used by a "fine" ADC (FADC). The FADC employs a multi-stage interpolation architecture, and amplifies the input signal minus reference signal to find the point at which the sign changes with sufficient accuracy. Since only the zero-crossing is important, this amplification is open loop, and does not need to be linear with an accurate gain, and therefore a closed loop amplifier with a high open loop gain is avoided. Univ. of Texas/Austin SRC Contact: W. Dale Edwards (Dale.Edwards@src.org)
Technical Thrust: Integrated System Design Research Highlight: Existing On-Chip Monitoring Approaches: Associated Interconnect Techniques, and Design Methodologies Recent systems-on-chip employ a variety of on-chip monitors to ensure correct system functionality. This report elaborates on existing approaches to on-chip monitoring used in current day SoCs. These monitors require interconnection and the use of a centralized controller. This report gives a detailed description of various existing monitors and their implementations. This is followed by previous work that has focused on monitoring based control. To better illustrate interconnect challenges, various network-on-chip techniques and associated design methodologies are described. Univ. of Massachusetts SRC Contact: David C. Yeh (email@example.com)
Interconnect & Packaging Sciences
Technical Thrust: Back End Processes Research Highlight: Electron Transport Size Effect and Joule Heating in Nanoscale Metallic Interconnects Embedded in Novel Low-k Dielectric Materials The most recent work of this task focused on the procurement of the thermal conductivity of thin film dielectrics and metals using the 3w method and Scanning Joule Expansion Microscopy (SJEM), respectively. The silicon wafers were provided by industrial partners. The fabrication of the metallic heaters took place in the Georgia Tech Microelectronics Research Center. With the new dielectric material provided by a member company, the previous clean room fabrication process was not possible, and a new process had to be discovered. Thus, several fabrication attempts were made using various fabrication parameters, none of which have been successful so far. However, when fabricating structures for SJEM, success was achieved by using a different dielectric material, which allowed the traditional fabrication method. Successful SJEM measurements were taken for both aluminum and copper samples. With this data, the thermal conductivity for these metals can be determined for a length scale of ~100nm. Georgia Institute of Technology SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Electron Scattering at Rough Cu-Barrier-Layer Interfaces In this report, first principles calculations of the barrier effect on the rough surface scattering is presented, with several coating materials: Al, Pd, Pt, Ta, Ir, etc.. Rensselaer Polytechnic Institute SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Incorporation of Finite Thickness Traces into UA-FWLIS In modern high-speed interconnect packaging applications, the off-chip conductor thickness is often times comparable with the trace width. Therefore it is desirable to handle the thickness of the traces. In this report, the authors summarize a procedure for extending UA-FWLIS so that it can handle finite thickness traces. By initially assuming PEC conductors, the traces can then be replaced by four surface current sheets on their four surfaces. Then new reactions are derived to handle the
vertical current sheets. The initial results of the new finite thickness trace model are then compared with the ones from the zero thickness trace model. Univ. of Arizona SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Plasma Equipment and Process Modeling This report includes updates to HPEM include full Maxwell solver, updates of nonPDPSIM include Plasma Chemistry Monte Carlo Module for Ion Energy Distributions, reporting on IEADs in wafer-focus ring gap, and reporting on Plasma ALE. Iowa State University SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Report on the Signal Optimization Protocols for Raman Spectroscopy Analysis of the Interface Region between Dielectric and Encapsulation Layers in Interconnect Structures Raman signal optimization for blanket and patterned test structures was investigated utilizing a new nanoRaman tip-probe consisting of a Au-coated Ag nanoparticle mounted on a bent SiO(2) capillary. In baseline performance studies on strained SOI test structures the new nanoRaman probes demonstrated, on average, superior Raman tipenhancement and substantially improved lifetime in the Ar-ion laser probe beam. These tips were utilized for nondestructive "top-down" Raman probing of a Cu/SiCOH BEOL test structure to evaluate efficacy of investigating process-induced modifications to the SiCOH dielectric. Specifically, sample spectra were evaluated with respect to a variety of Si-C, Si-O, Si-O-Si, and Si-CH(3) stretch or bend peaks. Although Raman features associated with these spectral regions were clearly evident, the presence of interference effects and depth-resolution issues strongly suggest that a cross-sectioning approach be developed to directly probe dielectric/metal interfaces. An alternate approach would be to employ the surface-sensitive nanoRaman approach directly after CMP to optimize spectral signals from modified regions of the dielectric. Univ. at Albany - SUNY SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Tailoring NiSi Surface Chemistry for WNx ALD: Oxidation, Precleaning, and Precursor Interaction The purpose of this task was to characterize the surface chemistry of NiSi oxidation, precleaning and subsequent WF(6) CVD to produce a W/WNx overlayer. Studies during this first year focused primarily of oxidation in atomic vs. molecular oxygen environments. Studies have also characterized the interactions of WF(6) with clean NiPtSi surfaces (Pt doped NiSi, 5 atomic wt. %). Experiments typically involved (1) producing an atomically clean, stoichiometric (monosilicide) surface under UHV conditions by a combination of Ar ion sputtering, annealing and XPS characterization; (2) transfer under UHV conditions to a reaction chamber for oxidation or WF(6) reaction studies, and (3) transfer back to the analysis chamber under UHV conditions for further XPS characterization. Univ. of North Texas SRC Contact: Harold H. Hosack (Harold.Hosack@src.org) Research Highlight: Report on the Demonstration of Molecular Dynamics Simulations of Ion-surface Interactions of Model Nanoscale Features Molecular dynamics (MD) simulations of ion-surface and radical-surface interactions of silicon surfaces to model etching of 1 nm and 2 nm diameter hole shape evolution were conducted with Ar+ only; Ar+/F; CF(2)+ and
CF(3)+ ions. Rare gas ions only resulted in limited etching; addition of F atoms allowed continuous etching with some sidewall loss. Fluorocarbon CF(2)+ and CF(3)+ ions allowed a continuous etching with minimal sidewall loss. In all cases, the region surrounding the hole corresponding to the 1- 2 nm thick sidewall 'passivation' formed due to ion and radical interactions that originated at the hole bottom. Univ. of California/Berkeley SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Fundamental Studies of Plasma-Surface Interactions This final report summarizes the results obtained in the study entitled: Fundamental Studies of Plasma-Surface Interactions. Univ. of California/Berkeley SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: The Efficiency of CO(2) In Situ Ash Processes on Photoresist Stripping and Their Influences on ULK Materials Modifications The authors have examined the feasibility of CO(2) as source gas for in situ photoresist (PR) ash processes compatible with ultralow-k (ULK) materials, and performed characterization of 193 nm PR ash along with ULK (JSR LKD 5109) damage (removal of carbon from SiCOH films) evaluation. In situ PR ash processes are attractive because of high integratability with plasma etching processes. Results of both blanket film studies and actual pattern transfer/PR ash processes performed with PR patterned ULK are reported. Reduced pressure increased the ion density which led to a high PR ash rate (substrate at 10oC, line-of-sight interaction), while suppressing ULK damage (nonline-of-sight interaction). Low chamber pressure using CO(2) enabled a high RP ash efficiency (AE) which is defined as the amount of PR removed over the amount of ULK damaged (for a given time). AE using CO(2) is ~3 times improved relative to using O(2) due to low density of atomic oxygen which showed strong relationship with ULK damage. For low pressure CO(2) discharges and argon (Ar) addition, the ion density was increased by Ar addition, but did not increase the PR ash rate. However, the lower atomic oxygen density reduced the ULK damage directly. As a result of the faster reduction of ULK damage as compared to the PR ash rate, Ar addition to CO(2) increased AE. The team found that applying an RF bias to the substrate during in situ PR ash allowed enhancing the PR ash rate and remove organic residues more effectively than without RF bias. Due to the higher PR ash rate, the process time and exposure time of ULK trench sidewalls to the plasma was shortened. This resulted in reduced ULK damage relative to process conditions without RF bias. For etching/in situ PR ash sequential processes, a strong interaction of the processes was observed. Fluorocarbon (FC) plasma used for etching dielectric materials left FC residues on the chamber walls of the reactor. This FC deposit was released into the plasma during the in situ CO(2)-based PR ash process. The addition of fluorine to the gas phase environment made the plasma more aggressive in terms of both PR ash and ULK damage introduction. The PR ash rate thus increased, especially for high pressure operation. During FC plasma etching also a thin FC film was deposited on the ULK trench sidewalls (~1-2 nm for our gap structure simulation of trench sidewall processes). The authors found that this FC film could stand up to the CO(2) PR ash environment and provided efficient protection of the underlying ULK material exposed to the plasma without direct energetic ion bombardment. Univ. of Maryland SRC Contact: R. Scott List (Scott.List@src.org)
Research Highlight: Etching Kinetics and Surface Roughening of Low Dielectric Materials in Fluorocarbon Plasma The effect of film composition on etching yield was studied. It was found that the porous films exhibit more sputtering etching than oxide. It is likely, but not yet proven that this is in part a result of Si-C bonding which occurs during porous film formation. Films with higher methyl group content exhibits more sputtering behavior which may be a result of greater Si-C bonding in these films. The variation of roughening with film composition and off-normal angles were measured. All porous films exhibit smooth-roughened-smooth with the ion angle from normal incidence to grazing angle. For porous films with methyl groups, roughness appears to be transverse to the ion beam direction at 40 , then changes to be parallel to the ion beam at 75 . Low-k films with high carbon content has greater propensity to roughen and get maximum roughness at higher grazing angles The mechanism of roughening with increasing C/F ratios and decreasing Si/O ratio on the surface with off-normal angle, suggests a greater polymerization on more porous surfaces. It is believe that the greater porosity in the film initiates local polymerization causing micromasking which enhanced the roughening. Mass. Institute of Technology SRC Contact: R. Scott List (Scott.List@src.org)
Technical Thrust: Packaging Research Highlight: Measuring Fluidic Instabilities Due to Boiling with Varying Heat Distribution and Heat Flux in MEMS Fabricated Parallel Microchannels Heat sinks for next generation microprocessors must remove increasing levels of power with non-uniform spatial distribution (hotspots). Two-phase convection promises strongly reduced pump size but is challenging because of boiling flow instabilities. This work studies parallel microchannel boiling stability using a series of dual channel devices which are fabricated with varying lateral thermal resistance and integrated heaters and thermometers. The data are consistent with a demand curve analysis predicting flow distribution and wall temperatures in thermally isolated parallel channels with strictly fluidic interaction. Increasing the thermal resistance between two parallel channels is shown to strongly influence the onset of instabilities and adversely increase the peak temperature. These dual-channel experiments capture the key physics of multi-channel instabilities and provide the foundation for improved design of two-phase microfluidic heat sinks. Stanford University SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Fabricating Parallel Microchannel Samples With and Without Thermal Isolation Between Channels to Study the Effect of Thermal Crosstalk Between Parallel Channels and its Role Stabilizing or Destabilizing Specific Fluidic Interactions In microchannel boiling flow heat sinks, the thermal and fluidic interactions between parallel channels dictate operational stability but have been difficult to characterize. Previous measurements in systems with many parallel channels note a premature dryout failure, but are too complex to isolate instability mechanisms. In this work thermal and fluidic coupling are isolated with a progression of dual channel structures with varying lateral thermal resistance. MEMS fabrication in Silicon enables precise control over microscale dimensions and addition of integrated sensors and heaters which mimic microchip hotspots. Identifying the roles of thermal
and fluidic interaction between channels may enable design of an operationally stable boiling flow heat sink. Stanford University SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Creating Conjugate Heat Transfer Model of Parallel Microchannels with Compacted Empirical Correlations for Boiling and Two-phase Flow Microchannel heat sinks promise high heat flux cooling with minimal pumping power, but coupled thermal and fluidic interactions are complex and difficult to isolate. This work proposes a simplified model of a tractable system, enabled by novel experimental structures that can validate intermediate results. A compact model of boiling flow is fitted with empirical data from a single channel. For parallel channels, the single channel model is surrounded by an algorithm that calculates heat conduction in the substrate and flow distribution between channels. A demand curve analysis is proposed to inform the flow distribution algorithm. With the model validated in a simplified system, the behavior of more complex multi-channel systems can be predicted. Stanford University SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: High Fidelity Ultra-broadband Characterization Suite for the Measurement of Low Loss Dielectrics: Circular PC Board Approach The complex permittivity of dielectrics plays important roles in the modeling, design, fabrication and testing of microwave circuits, high speed digital systems and bio-medical applications. Accordingly, extensive research has been conducted in the past decades. To date, the popular measurement techniques in the RF and microwave region are cavity resonator, transmission line, free space and open-ended coaxial probe, among others. Each method has its unique pros and cons. For instance, the advantage of high Q resonant method is its high accuracy; but the measurement can only be performed at a single frequency for each laboratory setup. Recently, a broadband split cylinder resonant technique is reported, which is nondestructive. Nevertheless, the method is quite complicated in terms of apparatus and operations. Transmission line technique, as a nondestructive approach, seems to be simple for broadband characterization. However, it lacks precision. The free-space technique may suffer from electromagnetic interference; while the open-end coaxial probe method may not be suitable for extremely low-loss materials. Arizona State University SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Report on the Prototype Resonator and Performance Characteristics This report outlines: a) the fabrication of device-level, vacuum-cavity packages without resonators b) the fabrication and characterization of MEMS resonators without packaging. The packages were found to survive to over-molding process. The resonators showed RF characteristics of 2.1265 MHz resonant frequency with a Q factor of approximately 50. The vacuum-cavity packages and the resonators were fabricated in the clean room at University of Texas at Arlington. Univ. of Texas/Arlington SRC Contact: R. Scott List (Scott.List@src.org)
Research Highlight: Report on Fast, Nonlinear, Time-domain Integral-equation Solvers with SPICE Compatibility, for System-level EMI/EMC Analysis, Accommodating Multiple Spatial Scales A new time domain integral equation (TDIE) solver that permits fast and accurate system-level EMI/EMC analysis was developed. Three features were added to a marching-on-in-time (MOT)based TDIE solver pertinent to the analysis of interconnect structures developed under prior SRC funding: (i) A multiple, variable, and flexible time step capability; (ii) a low frequency timedomain adaptive integral kernel, and (iii) a spectral preconditioner that leverages hierarchical basis functions. Together, these features permit the analysis of complex system level EMI/EMC phenomena not possible using other time-domain solver technologies. The new solver is compatible with standard, SPICE-like simulators and with the scalable macro-models being developed under this Task. This report focuses on progress w.r.t. effort (iii) achieved during the past 12 months. Univ. of Illinois/Urbana-Champaign SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Multimode Interconnect (MMI) This slide set presents a summary of accomplishments in the first year of this contract. These are as follows: 1. Demonstration of this concept in a board level prototype, 2. Detailed simulation verification of a complete channel, 3. Design of a complete TX circuit, and an RX system, 4. Established design procedure for microstrip and 5. Determined theory for quantifying crosstalk between multimode bundles. North Carolina State University SRC Contact: R. Scott List (Scott.List@src.org)
Technical Thrust: Factory Systems Research Highlight: cRSM Software Documentation This report actually documents the entire cRSM Software prototype. The prototype software implements the methodology and the algorithms developed in the NSF/SRC/ISMI FORCe project Multi-Product Cycle Time and Throughput Evaluation via Simulation on Demand. This implementation provides its functionality in three components: The cRSM Generator, the Query Engine, and a relational database operating in the background accessible to both of these. Arizona State University SRC Contact: Alan Allan (firstname.lastname@example.org) Research Highlight: cRSM Software Documentation The title of the report on the web site is actually too narrow. This report actually documents the entire cRSM Software prototype. The prototype software implements the methodology and the algorithms developed in the NSF/SRC/ISMI FORCe project Multi-Product Cycle Time and Throughput Evaluation via Simulation on Demand. This implementation provides its functionality in three components: The cRSM Generator, the Query Engine, and a relational database operating in the background accessible to both of these.
Northwestern University SRC Contact: Alan Allan (email@example.com) Research Highlight: Study of Control Friendly Scheduling Methods This document reviews work on a control friendly scheduling method to aid in the integration of advanced process control (APC) systems with tool level scheduling systems. Single and multi-tool causal, state space models are developed for a multi-product system. A run varying Kalman filter gives: 1) estimates of tool and product states for feedback control purposes and 2) an estimate error covariance matrix, P. By projecting P for future runs, a processing order that provides improved process control performance is determined for the products in queue. The control friendly heuristics give improved estimation over traditional dispatching and EWMA control methods. Univ. of Texas/Austin SRC Contact: Alan Allan (firstname.lastname@example.org) Research Highlight: Scheduling with Advanced Process Control Constraints This document reviews two parts of work on production planning and scheduling in a semiconductor manufacturing system. The first part proposed two approaches to coordinate planning and scheduling combined with different WIP-control policies. Simulation results are used to test the proposed approaches under different scenarios of machine breakdown and demand variation. The second part tries to achieve the tradeoff between shop-floor scheduling and advanced process control (APC). Optimal solutions have been found for some special cases. The problem is proved to be NP-complete, and an effective heuristic algorithm is proposed for a single-machine problem. Univ. of Texas/Austin SRC Contact: Alan Allan (email@example.com) Research Highlight: Develop a Fab-wide Electrical Parameter Control Algorithm A fabwide electrical parameter control algorithm to directly control electrical parameters is developed. The algorithm uses available data and a process model to predict electrical parameter values. If the predictions are significantly off target then optimal set points for the later processing steps are calculated. A simple implementation with a least squares process model is evaluated and its limitations are discussed. The use of a PLS model is proposed to address some of the limitations faced in real manufacturing environments and its usefulness and limitations are evaluated. A cost function approach and a Bayesian method are also developed and discussed. Univ. of Texas/Austin SRC Contact: Alan Allan (firstname.lastname@example.org)
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