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    Memory Technology Forecast

      Dec 14, 2021

    VLSIinsiders' cloudside chat - December 14, 2021

    This week Dan Hutcheson and Dr. Choe discuss the latest technology trends in memory semiconductors. We cover Micron’s groundbreaking 176L NAND chip, as well as what he’s seen with Kioxia's chips. Then we look at how EUV is making its way into DRAM as well as R&D efforts with 3D-DRAM, such as capacitorless and vertical transistor technology.

    Jeongdong Choe, Ph.D. is a Senior Technical Fellow at TechInsights and is an expert in memory technology.

    About VLSIinsiders: Every week our analysts have a cloudside* chat to discuss current events and key issues of concern while sharing what they’ve heard over the past week from the semiconductor industry insiders. 
    * cloudside chat: A fireside chat without the fire and is across the clouds of the internet

    Other VLSIinsiders


    VLSIinsiders' Cloudside Chat — December 14, 2021

    Dan Hutcheson: Welcome to the VLSIinsiders. This is Dan Hutcheson and today I got Dr Choe, who is TechInsights’ memory expert. He does some amazing things with stuff. He's written some, you know, really in-depth reports. And in fact, he usually likes to talk for an hour. I'm going to have him sitting here trying to get just do 10 minutes and pack it all in 10 minutes. So how are you doing today, Dr. Choe?

    Dr. Choe: Good. Yeah. I am good.

    Dan Hutcheson: So why don't we start off and talk about NAND? You know, you did this report on Micron, and you know the 176-layer? Maybe in your own words, you could try to tell me why you thought that was so important.

    Dr. Choe: Yeah, as for Micron’s 176-layer actually is kind of a disruptive technology, even for the market and technology viewpoints, because they are the first one from the industry to make more than 150 layers. And because actually, sometimes ago, we thought that the set current, I mean, the string current might not be good for more than 100 layer, or 150 layers. I mean, there is not enough to operate that. But now, 176-layer means the 195 gates stack.

    Dan Hutcheson: So, close to 200.

    Dr. Choe: Yeah, almost 200. It's an amazing one and towards...

    Dan Hutcheson: So why do you need all the extra layers if it's just 176?

    Dr. Choe: Yeah, extra layers used for the dummy layers and interface, tag interface layers, and also the selectors from the source side and the tray size. So altogether, in total 195 layers, almost 200 layers there. It's an amazing one. Yeah.

    Dan Hutcheson: And then you have to drive current across all that, right?

    Dr. Choe: Yeah, right.

    Dan Hutcheson: So that, alright, I think you said that was the big challenge.

    Dr. Choe: Yeah, it's a big challenge because currently, we use the silicon tenor for vertical tenor horse. But you know that, you know, a decade ago, four decades ago, we used the 2D-NAND with a single crystal silicon tenors with high mobilities for electrons. But now, although we use the electron by carriers, but the silicon is kind of a polysilicon, not a single crystal silicon, so there's a lot of scattering issues and mobility reduction there. So, it's quite difficult to make a very high current in that area, but still silicon NAND, they can use some auditioner or conditioner way to increase the mobility like to find the grain size, or the kind of germanium added to silicon tenors or something like that to increase that current. But anyways, for up to date, 176 a layer device, it works and that makes us to prepare more and more layer, 30 NAND device more than 200 or more than 300 layers.

    Dan Hutcheson: Do you think that you have visibility that you think we can get to 400, 300, 400 layers then?

    Dr. Choe: Yeah, right. Although we can use the multideck like three decks or four decks. Intel already announced the three decks, but Samsung used steer single extreme single decks for they're one of the 20 layers, but for 230 or 40 something layers, Samsung can use the just two decks. That’s all. Yeah.

    Dan Hutcheson: Yeah. So, you know, the advantage of using a single deck, the more you can make it longer with a single deck, because it is more cost advantage, right? As opposed to stacking deck...

    Dr. Choe: Yeah! And also, Samsung decreased the data stack numbers and also the gate height, a particular height. So, this dependency but Intel or Micron or SK Hynix, their particular channel high aspect ratio, I mean is quite higher than the Samsung's.

    Dan Hutcheson: Why don't we switch topics and talk about DRAM a bit. What's going on there? What do you see exciting happening there?

    Dr. Choe: Yeah, a lot of happenings there actually, especially for last year, and this year. We see the EUV product from Samsung. They use the one degeneration, they used EUV for their B9 patterning landing pads and also the M one. So, we know that their upcoming one eight-generation, probably they used 4 or 5 additional EUV layers, including active layers and also capacitor patterns there. So, it's an amazing one, quite different from the Micron. But you know that Micron 1-alpha already released on the market is the for the first time from industry and already commercialised for the DRAM team devices as well. So, yeah.

    Dan Hutcheson: Micron has always been good at using litography technology and pushing their lithography a generation or two ahead of everybody else. But Samsung, don't they have an advantage in the fact that they have a fall-back strategy with EUV that they could always use it for logic too, right?

    Dr. Choe: Yeah, right. So, Samsung, especially Samsung, now they have founded a business for  logic device, like five nanometres or three nanometres. So that's why they have some flexibility to use the EUV for DRAM and the logic as well. So that's why they got to use the EUV for the DRAM device since one degeneration different from SK Hynix, or some Micron. And then maybe they can keep the EUV technology for more than five or six generations on DRAM because although they adopt the 3D-DRAM or the 4X care DRAM or two to one T-DRAM, but they can use the EUV generation for one A, one B, one C, one D, or zero A, zero B, something like that. So more than five generations, they can use that. Yeah.

    Dan Hutcheson: Yeah. Yes, absolutely. Samsung basically got ABCD.

    Dr. Choe: Yeah. Compare to Micron…

    Dan Hutcheson: We got X, Y, Z.

    Dr. Choe: Yeah, right.

    Dan Hutcheson: Pretty fun. So well, there's, you know, as we start to look at that, do we, the big challenge of DRAM has been that you can't keep enough electrons in the capacitors, the capacitor gets smaller and smaller, and you try going to these high K dielectrics or no excuse me locate the solver and then and then the, but what about other technologies like capacitors versus DRAM.

    Dr. Choe: Actually, the most important thing for the DRAM side is how to increase the speed, means the TRC, so how to increase the capacitor and how the capacitance and how to reduce the parasitic capacitance like that. So, to do this, actually, we need some innovative technologies such as the air gap process or air space process between load and also for high K dielectric materials for capacitors, that capacitors with a very thin layer to increase the cell capacitance. And also, maybe we can use the STO with the retention electrode in the near future for DRAM products. And also, you can use the 3D Stack DRAM, or 3D one 3D-DRAM or two 3D-DRAM without capacitors in the future.

    Dan Hutcheson: Sounds pretty good. What about three? Okay, so as we go to 3D-DRAM is, when do you think that can happen? Because you were, I think you think it's a pretty tall wall to climb. It's a pretty difficult technology, isn't it?

    Dr. Choe: Yeah. So, for example, firstly, for 3D-DRAM that we can consider a lot of different prototypes, for example, data structure and B9 structure and then capacitor structure on stack. And then multiple stacked capacitors with multiple meshes like capacitor one, capacitor two, capacitor three, something like that to read the second pistons, but it's, it's four scares can make you can prepare four scare or six scare with this one. Or maybe we can use the one T-DRAM without capacitor or two T-DRAM without capacitor like... I just thought something like that some different materials we can use that and also some particular gate, so-called the VZ. Yeah. So-called. A particular gate to DRAM structure, totally different from the current PK, or YK structure. Yeah.

    Dan Hutcheson: Yeah. So, when you say the vertical gate; you basically put the source, no vertical flow that the information so that you have the source underneath the gate and the drain, or are you talking about?

    Dr. Choe: I'm talking about the source and gate and the drain in a particular direction. Yeah.

    Dan Hutcheson: Because I know IBM just had a paper on that.

    Dr. Choe: Yeah.

    Dan Hutcheson: ADM.

    Dr. Choe: Yeah.

    Dan Hutcheson: So, you can use that as a DRAM technology. That's very interesting.

    Dr. Choe: Yeah. In the future. Yeah.

    Dan Hutcheson: Yeah. Well, thanks for taking the time today. I really appreciate it.

    Dr. Choe: Thank you so much, Dan!